1. Field of the Invention
The present invention relates to a substrate treatment method of forming a resist pattern over a substrate, a non-transitory computer storage medium, and a substrate treatment system for executing the substrate treatment method.
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2013-44427, filed in Japan on Mar. 6, 2013, the entire contents of which are incorporated herein by reference.
2. Description of the Related Art
In a photolithography process in a manufacturing process of a semiconductor device, for example, a resist coating treatment of applying a resist solution onto a film to be treated on a surface of a semiconductor wafer (hereinafter, referred to as a “wafer”) to form a resist film, exposure processing of irradiating the resist film over the wafer with light in a predetermined pattern to expose the resist film, a developing treatment of developing the exposed resist film and so on are performed in sequence to form a predetermined resist pattern over the wafer. Then, after the resist pattern forming treatment, the film to be treated is etched using the resist pattern as a mask, whereby a predetermined pattern is formed in the film to be treated.
Semiconductor devices in recent years are miniaturized to be, for example, 20 nm or less, and the aforementioned resist pattern is required to be miniaturized. With the resist pattern in the current state, however, there is a limit to increasing the etching selection ratio with respect to the film to be treated and thus it is becoming difficult to ensure the accuracy of the etching technique.
Hence, it is proposed that a silicon film achieving a high etching selection ratio with respect to the film to be treated is formed under the resist film in order to improve the accuracy of the etching technique (Japanese Translation of PCT Application Publication No. 2003-519434). In this case, after the photolithography processing is performed to form a resist pattern in the resist film over the wafer, the silicon film is etched using the resist pattern as a mask, whereby a predetermined pattern in the silicon film. Thereafter, the film to be treated is etched using the pattern of the silicon film as a mask.
Incidentally, along with the above-described miniaturization of the resist pattern, the aspect ratio of the resist pattern increases to easily cause a so-called pattern collapse in which the resist pattern tilts to collapse. In this regard, in the method discussed in Japanese Translation of PCT Application Publication No. 2003-519434, the etching for the silicon film is performed using the resist pattern as a mask, so that there is a possibility that the pattern collapse occurs. Further, in the case of etching the film to be treated using the method described in Japanese Translation of PCT Application Publication No. 2003-519434, it is necessary to form the silicon film and etch the silicon film, thereby making the process of wafer treatment complicated.